The present invention relates to semiconductor devices and manufacturing technologies thereof and in particular to a technology effectively applicable to a resin-sealed semiconductor device and a manufacturing technology thereof.
Japanese Unexamined Patent Publication No. Hei 6(1994)-132457 (Patent Document 1) describes a structure in which a thick transistor placement portion and thin inner leads are separately configured. According to Patent Document 1, a transistor element is placed over a transistor placement portion and this transistor placement portion and inner leads are joined and integrated with each other by inserting a dowel (joining portion) into a hole and swaging it. As illustrated in FIG. 5 in Patent Document 1, the transistor placement portion and the inner leads are sealed with sealing resin so that it is completely covered.
Japanese Unexamined Patent Publication No. 2000-31338 (Patent Document 2) describes the structure illustrated in FIG. 2 and FIG. 6 in Patent Document 2. In this structure, a lead frame is placed over a base substrate with a resin insulating layer in between and a switching semiconductor element is placed over this lead frame.    [Patent Document 1]    Japanese Unexamined Patent Publication No. Hei 6 (1994)-132457    [Patent Document 2]    Japanese Unexamined Patent Publication No. 2000-31338